Engine Sensor Simulation Card
What is the Engine Sensor Simulation Card?
The Engine Sensor Simulation Card is a customized version of Concurrent’s programmable FPGA card specially designed for hardware-in-the-loop engine control unit (ECU) testing. The card and its associated firmware can support two- and four-cycle engines with up to sixteen cylinders and four independent, variable-phase camshafts. Engine speeds up to 30,000 rpm with 0.001 rpm resolution can be simulated along with crank reverse rotation (idling stop).
In HIL engine testing, an ECU is connected to a real-time simulation computer that executes the engine model and evaluates the ECU’s operation. An engine ECU handles a wide variety of input and output control signals that perform on the microsecond level. A single high-performance FPGA card, with its customizable firmware, can often provide an interface to the ECU that would otherwise require multiple standard data acquisition cards. An FPGA I/O card can also buffer ECU events to provide improved performance communication to and from the simulation model.
Specifications
Crank-Angle Sensor Signal Generation
| Pattern Configuration | Arbitrary pulse pattern configuration with less than 0.006° CA resolution at +30,000 RPM |
| Waveform Generation | Identifiable by crank reverse rotation |
| Output | Phase Multi-level voltage output; shifting (A/B-Phase); pulse frequency modulation |
Cam-Angle Sensor Signal Generation
| Pattern Configuration | Arbitrary pulse pattern configuration with less than 0.006° CA resolution at +30,000 RPM |
| Waveform | Up to 4 shafts |
| Synchronization | With crank angle |
| Variable Command | Individual phase variable command for all shafts (resolution 0.01° CA) |
Ignition and Fuel Injection Signal Acquisition
| Inputs | Up to 16 channel |
| Timing | Acquire leading/trailing edge timing of crank-angle sensor base |
| Pulse Width | Min. 50 nanoseconds; multiple pulses can be buffered |
Hardware
| 96-channel Digital I/O | 5V 4mA TTL; digital I/O direction per nibble; high speed digital isolators |
| D-to-A Output | Single-ended 16-channel 16-bit |
| D-to-A Output Voltage | 0 to +10V, +/-5V or +/-10V |
| D-to-A Output Update Rate | 100K updates/second per channel |
| D-to-A Output Details | Range selection; 10 Milliamp output drive |
| A-to-D Input | Differential or single-ended 16-channel 16-bit |
| A-to-D Input Voltage | +/-5V or +/-10V Input Range |
| A-to-D Update Rate | 300K updates/second per channel |
| Altera Arria V Family FPGA | 362K logic elements |
| DRAM | 1GB |
Features
| Clock Source | TCXO |
| Clock Generator | 8-output programmable |
| Connectors | RJ-45 synchronization; Industry-standard high density SCSI 68-pin connectors |
| PCI | PCIe x4 Revision 1.0a |
| Isolated Power | All I/O |
| NIST Traceable Calibration | Optional |
Packaging
| Dimensions | FHFL PCI Express (12.3" long x 3.8" high) |
Power Requirements
| Without External Connector | Up to 25 watts |
| With External Connector | Up to 60 watts |
Environmental
| Operating Temperature | 10° to 40° C |
| Storage Temperature | -40° to 65° C |
| Relative Humidity | 10 to 80% non-condensing |
| Cooling | Forced Air Required |
| Other | ROHS Compliant |
Ordering Information
| Engine Sensor Simulation Card | CP-ENG-SIM |
| RedHawk Linux Driver | WC-CP-FIO |
| SIMulation Workbench License | ICS-SWB-1277 |
| 1-meter cable | CX-CBL-HSI-F-01 |
| 2-meter cable | CX-CBL-HSI-F-02 |
| 3-meter cable | CX-CBL-HSI-F-03 |
| Breakout Module | CX-CBL-AIO-BRKF |
