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Engine Sensor Simulation Card

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What is the Engine Sensor Simulation Card?

The Engine Sensor Simulation Card is a customized version of Concurrent’s programmable FPGA card specially designed for hardware-in-the-loop engine control unit (ECU) testing. The card and its associated firmware can support two- and four-cycle engines with up to sixteen cylinders and four independent, variable-phase camshafts. Engine speeds up to 30,000 rpm with 0.001 rpm resolution can be simulated along with crank reverse rotation (idling stop).

In HIL engine testing, an ECU is connected to a real-time simulation computer that executes the engine model and evaluates the ECU’s operation. An engine ECU handles a wide variety of input and output control signals that perform on the microsecond level. A single high-performance FPGA card, with its customizable firmware, can often provide an interface to the ECU that would otherwise require multiple standard data acquisition cards. An FPGA I/O card can also buffer ECU events to provide improved performance communication to and from the simulation model.

See the data sheet

Programmable FPGA Card

Specifications

Crank-Angle Sensor Signal Generation

Pattern ConfigurationArbitrary pulse pattern configuration with less than 0.006° CA resolution at +30,000 RPM
Waveform GenerationIdentifiable by crank reverse rotation
OutputPhase Multi-level voltage output; shifting (A/B-Phase); pulse frequency modulation

Cam-Angle Sensor Signal Generation

Pattern ConfigurationArbitrary pulse pattern configuration with less than 0.006° CA resolution at +30,000 RPM
WaveformUp to 4 shafts
SynchronizationWith crank angle
Variable CommandIndividual phase variable command for all shafts (resolution 0.01° CA)

Ignition and Fuel Injection Signal Acquisition

InputsUp to 16 channel
TimingAcquire leading/trailing edge timing of crank-angle sensor base
Pulse WidthMin. 50 nanoseconds; multiple pulses can be buffered

Hardware

96-channel Digital I/O5V 4mA TTL; digital I/O direction per nibble; high speed digital isolators
D-to-A OutputSingle-ended 16-channel 16-bit
D-to-A Output Voltage0 to +10V, +/-5V or +/-10V
D-to-A Output Update Rate100K updates/second per channel
D-to-A Output DetailsRange selection; 10 Milliamp output drive
A-to-D InputDifferential or single-ended 16-channel 16-bit
A-to-D Input Voltage+/-5V or +/-10V Input Range
A-to-D Update Rate300K updates/second per channel
Altera Arria V Family FPGA362K logic elements
DRAM1GB

Features

Clock SourceTCXO
Clock Generator8-output programmable
ConnectorsRJ-45 synchronization; Industry-standard high density SCSI 68-pin connectors
PCIPCIe x4 Revision 1.0a
Isolated PowerAll I/O
NIST Traceable CalibrationOptional

Packaging

DimensionsFHFL PCI Express (12.3" long x 3.8" high)

Power Requirements

Without External ConnectorUp to 25 watts
With External ConnectorUp to 60 watts

Environmental

Operating Temperature10° to 40° C
Storage Temperature-40° to 65° C
Relative Humidity10 to 80% non-condensing
CoolingForced Air Required
OtherROHS Compliant

Ordering Information

Engine Sensor Simulation CardCP-ENG-SIM
RedHawk Linux DriverWC-CP-FIO
SIMulation Workbench LicenseICS-SWB-1277
1-meter cableCX-CBL-HSI-F-01
2-meter cableCX-CBL-HSI-F-02
3-meter cableCX-CBL-HSI-F-03
Breakout ModuleCX-CBL-AIO-BRKF

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